Applied Technologies and Innovations

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Volume 4
Issue 1
Online publication date 2011-04-18
Title Algorithm for micropipeline buffer control
Author Dimitar Tyanev, Violeta Bozhikova, Stefan Gerganov, Bozhidar Georgiev
Abstract The paper focuses on the problem of hardware implementation of computational process containing conditional transitions. Asynchronous organization of pipelines at microoperational level is provided for the hardware. Its characteristic feature is that it includes both one and multi-cycle micropipeline units. Because of these circumstances, the outgoing pipeline results do not correspond in the same order to the tasks running in the pipeline. The article presents the synthesized original logical structure of the micropipeline buffer and a specific to its service strategy through which their correct order is restored when reading results from the buffer. Another programming model of the structure of the buffer is described, by which its behavior was studied in different possible situations. In addition, a programming model of the structure of the buffer was created and its behavior in different possible situations is examined. The results of numerical experiments with the programming model are presented. Based on them recommendations are formulated about the parameters of the buffer and the structure of the pipeline. 
Citation
References
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Tyanev, D., Kolev, S., Josifov, V., 2007. “Method for realization of self-controlling loop apparatus structures,” Proceedings of Technical University of Varna, 2007, ISSN 1311-896X, pp.130-35, http://www.tyanev.com/resources/docs/Document_V_42.pdf 

Tyanev, D., Kolev, S., Yanev, D., 2007. “Method for realization of self-controlling loop apparatus structures - part 2,” Computer Science and Technologies, Publication of Computing and Automation Faculty Technical University of Varna, Bulgaria, ISSN 1312-3335, V 2/2009, pp.23-30.

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Tyanev, D., Kolev, S., Yanev, D., 2010. “Race condition free asynchronous micro-pipeline units,” International Conference on Computer Systems and Technologies - CompSysTech’10, Sofia, Bulgaria, pp.31-37. http://portal.acm.org/citation.cfm?id=1839379.1839386&coll=DL&dl=GUIDE&CFID=166 49328&CFTOKEN=79928997

Tyanev, D., Popova, S., 2010. “Asynchronous micro-pipeline with multi-stage sections,” ICEST’2010, Ohrid, Macedonia.

Tyanev, D., Yanev, D., Kolev, S., 2009. “Method for realization of self-controlling loop apparatus structures,” Fifth International Scientific Conference Computer Science’2009, Sofia, Bulgaria, Proc.’2009, ISBN: 978-954-438-853-9, pp.154-158.

Hennessy, J., Patterson, D., 2003. Computer Architecture. A Quantitative Approach, 3rd Ed., Morgan Kaufman Publishers, ISBN 1-55860-596-7.

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Keywords Micropipeline, conditional transition, restore order, micropipeline buffer.
DOI http://dx.doi.org/10.15208/ati.2011.2
Pages 12-21
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